Please read the following sections from the AMBA AXI and ACE Protocol Specification - alternate link:
- Chapter A1
- Chapter A2, which is mostly about signal definitions. You don’t need to understand what all of the signals do at this point, but make sure that you do understand what the VALID, READY, ADDR, LEN, and SIZE signals do within each of the channels. For example, ADDR refers to the AWADDR in the Write Address Channel, and ARADDR in the Read Address Channel, and so forth.
- Chapter A3 (A3.1-A3.3), which is largely about protocol. Make sure that you understand how the handshaking works in each channel.
Study Questions
- How many transaction channels are in the AXI architecture?
- How many of the transaction channels are related to read transactions? How many are related for write transactions?
- What is the purpose of the Write Response Channel?
- What is the allowable minimum width for the read data bus? for the write data bus?
- What is the maximum allowable width for the read data bus? for the write data bus?
- (T or F) The master can perform write transactions without slave acknowledgement for previous write transaction.
- (T or F) AXI supports multiple address and data busses.
- (T or F) AXI channels are bidirectional.
- What is a register slice? What advantage do they provide?
- Why is it important that reset deassertion occur on the rising edge of ACLK?
- All 5 channels use the same VALID/READY handshake process. Please explain exactly when the handshake occurs.
- (T or F) A slave can assert a VALID signal.
- (T or F) A master can assert a READY signal.
- (T or F) The source can wait for the READY signal before asserting VALID.
- (T or F) The destination can assert the READY signal before a VALID signal arrives.
- Who (Master or Slave) sources AWVALID?
- Who (Master or Slave) sources RVALID?
- Who (Master or Slave) sources ARREADY?
- How many channels are involved in every read operation?
- How many channels are involved in every write operation?
- (T or F) The master can wait for the slave to assert ARREADY before asserting ARVALID.
- (T or F) The slave can wait for ARVALID to be asserted before it asserts ARREADY.
- Name the signals involved in the handshake for the Read Data Channel.
These are extra questions that can be ignored for the quiz but we may discuss them if we have time.
- (T or F) The slave can assert BVALID as soon as WVALID and WREADY are asserted. What is a “beat”?
- (T or F) The slave can terminate a burst if an error occurs.
- (T or F) The master can terminate a burst if an error occurs.
- (T or F) All bus transactions are bursts.
- How does the slave indicate the success or failure of a read or write transaction?