Building Hardware in Vivado

The Xilinx Vivado software allows you to create digital hardware circuits that can be programmed onto the FPGA. Some basics of Vivado:

  • The circuits are designed using hardware description languages (HDLs), such as Verilog or VHDL (as you may have done in ECEN 220).
  • Vivado contains an IP Repository, which is a collection of HDL modules that Xilinx provides to you. You are free to use these modules in your design.
  • Vivado provides a block diagram designer, called IP Integrator, which allows you to graphically connect the different modules in your design to make a complete system (The hardware system page shows the block diagram for the Vivado project we use in this class).

Accessing Vivado

Vivado is installed in the lab machines. Alternatively, you can download the Vivado tool on to your personal computer or VM.

Before you can run Xilinx tools, you must add them to your PATH (this must be done each time you open a new terminal):

source /tools/Xilinx/Vivado/2022.2/settings64.sh

Then you can run Vivado:

vivado

Note: There seems to be an issue with the Vivado installation in the lab that is causing this to fail. Instead, just run Vivado directly:

/tools/Xilinx/Vivado/2022.2/bin/vivado

Vivado Projects

Creating Projects

In Lab 5 you will need to create a project to simulate and verify your PIT module. You should have learned how to create Vivado projects in ECEN 220. If you want a refresher, you can go back and watch the video on the Creating a New Vivado Project page.

In ECEN 220 we had you escalate several Vivado warnings to errors, to help you catch common mistakes in your design. It would be a good idea to adjust these settings on your Vivado project by running these commands once on each new project:

set_msg_config -new_severity "ERROR" -id "Synth 8-87"
set_msg_config -new_severity "ERROR" -id "Synth 8-327"
set_msg_config -new_severity "ERROR" -id "Synth 8-3352"
set_msg_config -new_severity "ERROR" -id "Synth 8-5559"
set_msg_config -new_severity "ERROR" -id "Synth 8-6090"
set_msg_config -new_severity "ERROR" -id "Synth 8-6858"
set_msg_config -new_severity "ERROR" -id "Synth 8-6859"
set_msg_config -new_severity "ERROR" -id "Timing 38-282"
set_msg_config -new_severity "ERROR" -id "VRFC 10-3091"
set_msg_config -new_severity "WARNING" -id "Timing 38-313"
set_msg_config -suppress -id "Constraints 18-5210"

Block Design

For Lab 6 M1, you will need to create a block diagram based simulation project. In Lab 6 M2, you will edit an existing block diagram for the hardware on the board that you have been using up to this point in the class.

The block diagram feature of Vivado allows you to visually instantiate and connect different IP and hardware modules. Some things to note:

  • To create a block design, click Create Block Design in the left-side menu of Vivado. The block design should now show up in the Sources window.
  • To open an existing block design, click Open Block Design, or double click the .bd file in the Sources window.
  • A block design can be instantiated in HDL modules just like you would instantiate other HDL modules. An example is shown in the test bench provided on the Simulating AXI IP page. A block doesn’t can’t function as the top-level module for a Vivado project, so it is always instantiated in a a top-level wrapper module, or test bench module.
  • With a block design open, you can right click on empty space and click Add IP… to add Xilinx IP, click Add Module… to add a Verilog module you created (the Verilog file must already be added to the project sources), or Create Port… to create input/output ports.

Committing your Vivado Project to Git

You will want to commit your Vivado projects to Git. You shouldn’t attempt to commit the actual project files, as there are sometimes hundreds of files. Instead, you should follow these steps to generate a Tcl file that can be used to recreate your project.

  1. Vivado will attempt to save results of your synthesis run to avoid having to run it again when the project is recreated. We don’t want to save these, so we need to change a setting first. Right-click Synthesis in the left-hand menu and select Synthesis Settings. Locate the Incremental Synthesis option, and click the “…” box to change to Disable Incremental Synthesis. Click OK to save the setting.
  2. File->Project->Write Tcl
  3. Make sure to check the box Recreate Block Designs using Tcl.
  4. Specify a path to save your Tcl file.
  5. Commit the new Tcl file to Git.
  6. In the future, you can recreate your project by running vivado -source your_project.tcl

Updating the ECEN 427 Hardware

The hardware that you have been using for the labs up to this point is provided in a Vivado project included in the class repository. All of the necessary files are located in the hw directory.

Creating the ECEN 427 Project in Vivado

You don’t need to do this for Lab6 M1, only Lab6 M2.

The project can be created using the ecen427.tcl script. However, the project depends on at least one file that is too large to commit to Github, so it must first be unzipped. Unzipping the file, and running the ecen427.tcl script can be done in one step using a provided Makefile target:

cd hw
make

If you run this it should create the Vivado project and open the newly created project in the Vivado GUI.

Opening Your Existing Project

Creating the project only needs to be done once. In the future you can just do the following:

  1. Launch Vivado (vivado)
  2. Open your Vivado project, which should be listed under recent projects. If it isn’t listed there, you can always go to File->Open Project and browse to your Vivado project file (hw/ecen427/ecen427.xpr).
  3. Alternatively, you can run vivado hw/ecen427/ecen427.xpr

Compiling a new Bitstream

  1. The main function of the Vivado software is to compile your design to a bitstream. A bitstream (‘‘.bit’’ file) can be used to reconfigure the FPGA to implement your circuit. In Vivado, click Generate Bitstream. It will take several minutes to compile.
  2. The created bitstream, system_wrapper.bit, will be located in your Vivado project folder hw/ecen427/, in the subdirectory ecen427.runs/impl_1/. (It’s often a good idea to check the timestamp on the file to make sure it was indeed updated recently.)
  3. We provided you with a bitstream for the original hardware system, which is located at hw/ecen427.bit. After you change the hardware and generate a new bitstream, you need to replace this bitstream with your new one, before proceeding to the next step: 
    cd hw
cp ecen427/ecen427.runs/impl_1/system_wrapper.bit ecen427.bit

    or, more simply:

    cd hw
make ecen427.bit
  4. The PYNQ board requires the bitstream in .bin format. Go to the device_tree folder in the top-level of your repo, and run make build to create a new ecen427.bit.bin file. This uses the bootgen utility (a Xilinx program), so make sure you have the Xilinx tools sourced in your terminal.
  5. Push the new ecen427.bit and ecen427.bit.bin file up to Github.

Loading the new Bitstream on your PYNQ board

On your PYNQ board:

  1. Run git pull to get your new hardware files that you just pushed up to the repo.
  2. Go to the device_tree folder.
  3. Run sudo make install to copy the new ecen427.bit.bin file into the system directory that is used to configure the FPGA (/lib/firmware). This command will instantly load the new hardware, as well as overwrite the old bitstream, such that this new bitstream will be used anytime you reboot the board.