Each of you will have the opportunity to teach a portion of a class period. You will teach as a group of 3. Please sign up for a time/topic on Teams.
Guidelines and Suggestions
- Each mini-lecture should cover half of the class period. Plan for about 35 minutes, accounting for questions along the way.
- You can use power-point slides, the white board, handouts, or a combination of any of these.
- Make sure you prioritize student learning. Your goal is not simply to transfer the chapter text to Powerpoint slides and deliver the content. Consider how to best help students learn about these concepts. For example, you might want to experiment with these concepts in the Vitis HLS tool and share your experiences with the class, or do a live demo.
- You might not have time to cover all the material in the chapter. It is more important to do a good job covering the basics than to try and cram all of the content into your presentation.
- Look over the grading scheme below.
- There will inevitibly be some difficulty in “fitting together” the different presentations from the various groups. For example, the earlier chapters sometimes refer to concepts that will be covered in later chapters by other group’s presentations. Likewise, when presenting a later chapter, you may be unsure of what will be fully covered by earlier presentations. Just do your best, don’t feel like you need to cover every detail, and be flexible in your presentations and willing to adapt on the fly.
Topics
Select a chapter (chapter 2–12 only) from Parallel Programming for FPGAs. On this page you can find a link to the pre-built PDF. Please indicate the chapter you select on Teams. Each group should select a different chapter.
What to include
Your presentation should focus address each of these areas.
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What is the algorithm being accelerated, and how does it work? (This is your background information)
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What makes the problem suitable for HLS acceleration? Where there any modifications made to the algorithm or source code in order to make in more amenble to hardware acceleration? Why were these modifications mode? Was a certain certain algorithm class chosen because it works well for HLS acceleration?
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What HLS optimizations were applied? Why? Were they effective?
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(Optional) What is the bottleneck to making this algorithm faster? Is it resource bound? Memory bound?