Final Exam

The final exam will be comprehensive and cover all the material for the entire semester. The new material that will be covered on the final but not yet covered in a previous exam is the material from sections 5.6 through 5.13 and Chapter 6.

Exam Format

• The exam will be held in class on Tuesday, April 21st, 2026 from 7 am to 10 am.
• 45 multiple choice questions and one free response question (you must complete the free response question in pencil).
• Closed book
• Access to a personal calculator

The following tables and figures will be given on the exam:

• Instruction format diagrams
• Single-precision floating-point format
• Datapath diagram
• Rooftop diagram

Exam Preparation Suggestions

• Review and practice in class quizzes. Several of the problems are variations of existing quiz questions.
• Review homework questions. Some problems are variations of homework questions.
• Review the ‘Exam Review Questions’ listed below
• Review textbook (see review questions on areas of the textbook to review)
  • Some questions on the textbook may be given that are not explicitly covered in class
  • Topics not listed in the review questions will not be covered in the exam

Chapter 5

• Section 5.6 - Virtual Machines
  • What are system virtual machines?
  • What advantages do they offer?
  • What are the technical challenges in implementing them?
• Section 5.7 - Virtual Memory
  • What level in the memory hierarchy is used as a cache by virtual memory?
  • What are the benefits of virtual memory?
  • What address translation must occur in systems with virtual memory?
  • What is a page fault?
  • How is a specific page found in main memory?
  • What information is included in a page table?
  • Why are tag comparisons required to locate blocks in a cache, but not pages in main memory?
  • What is the advantage of multi-level page tables?
  • What is a translation-lookaside buffer (or TLB)?
  • What is included in each TLB entry?
  • Is a TLB miss the same as a page fault?
  • What happens in response to a TLB miss?
  • Why are protection bits (that limit certain kinds of accesses) usually included in page table entries and TLBs?
• Section 5.8 - A common framework for memory hierarchy
  • What are the 4 key questions in our text’s common framework for memory hierarchy?
  • What are the three types of misses in the three Cs model?
• Section 5.10 - Parallelism and Memory Hierarchies
  • What is the cache coherence problem in systems with multiple processors?
• Section 5.13 - Real Stuff: The ARM Cortex-A8 and Intel Core i7 Memory Hierarchies
  • What are the general characteristics of the Intel Core i7 and ARM A53 memory hierarchy?

Chapter 6

There will be some questions from Chapter 6 from the reading that may not have been covered in class. You should review the reading as part of your preparations for questions from Chapter 6.

• What is the meaning of the following classical parallel processing terms? SISD, SIMD, MISD, and MIMD
• Understand the meaning of and difference between the following terms related to parallel computing:
  • Computer cluster
  • Multicore microprocessor
  • Hardware multithreading
  • Vector architecture
  • VLIW architectures
• What is the difference between coarse grain, fine grain, and simultaneous hardware multithreading?
• What is the difference between shared memory and message passing multi core computing?
• What is Amdahl’s law and wow does Amdahl’s law apply to parallel processing?
• What is the difference between weak scaling and strong scaling?
• What are the differences between GPU and traditional CPUs?
• What is arithmetic intensity?
• What is a Roofline Model for parallel performance?