Exam #2

Exam Format

• The exam will be held in the testing center.
• Material covered: Chapters 3 and part of Chapter 4 (section 4.6 - 4.16).
• 25 multiple choice questions (15 for chapter 3 and 10 for chapter 4)
• Closed book
• You may bring your own calculator
• You may write on the exam
• No time limit on the exam (the average student takes about 1 hour to complete the exam)

Exam Preparation Suggestions

• Review the ‘Exam Review Questions’ listed below
  • These are not questions that will be put on the exam but questions that suggest what areas we discussed you should review. No question will be given on the exam that doesn’t relate to at least one of the questions below.
• Review homework questions
• Review textbook (see review questions on areas of the textbook to review)
  • Some questions on the textbook may be given that are not explicitly covered in class.
• Review in class quizzes

Chapter 3

• Section 3.2 - Addition and Subtraction
  • What does it mean for an arithmetic operation to overflow?
  • How can overflow be detected in the addition of unsigned numbers?
  • How can overflow be detected in the addition of signed numbers?
  • How can overflow be detected in the subtraction of signed numbers?
  • What happens in a C program when integer overflow occurs?
  • How do you perform 8-bit (char) and 16-bit (short) operations in the RISC-V 32-bit architecture?
• Section 3.3 - Multiplication
  • In general, what sequence of simpler operations is used to perform integer multiplication? <!– * Can you step through a multiplication example (with unsigned operands) using the hardware in Figure 3.3?
  • Can you step through a multiplication example (with unsigned operands) using the refined version of the hardware in Figure 3.5? –>
  • What general techniques can be used to produce faster multiplication hardware?
  • What multiply instructions are included in the RISC-V instruction set, and what does each do?
  • Can a shift instruction always replace an integer multiply by a power of 2?
• Section 3.4 - Division
  • In general, what sequence of simpler operations is used to perform integer division? <!– * Can you step through a division example (with unsigned operands) using the hardware in Figure 3.8?
  • Can you step through a division example (with unsigned operands) using the refined version of the hardware in Figure 3.11? –>
  • Why is it more difficult to speed up a hardware divider than a hardware multiplier?
  • What divide instructions are included in the RISC-V instruction set, and what does each do?
  • Can a shift instruction always replace an integer divide by a power of 2?
• Section 3.5 - Floating Point
  • What are fixed-point binary numbers and how do you convert to and from decimal numbers?
  • What are the conventions for representing normalized floating-point numbers?
  • How are the conventions differ for denormalized floating-point numbers? (See the summary in the class slides.)
  • Given the bit representation of a floating-point number, can you determine the decimal value it represents. (Okay to work with easy examples: 1, 256.5, -15/16, etc.)
  • How do you represent +0, -0, +infinity, and -infinity in floating-point? How do you represent “Not a Number” (NaN) in floating point?
  • Given a decimal value, can you determine its bit representation as a floating-point number?
  • What steps are required to add two floating-point numbers?
  • What steps are required to multiply two floating-point numbers?
  • What floating-point instructions are included in the RISC-V instruction set?
  • What do the floating-point comparison instructions do?
  • What registers do the RISC-V floating-point instructions operate on?
  • How do you round to the “nearest even”?
  • Why are floating-point addition and multiplication not associative and what challenges does this present?

Chapter 4 - part B

• Section 4.6 - An Overview of Pipelineing
  • What are real-world analogies for pipelining?
  • What is the benefit of pipelining?
  • Does pipelining reduce the time to execute one instruction, from start to finish (also called the latency)?
  • How does pipelining improve performance?
  • Under what conditions is the speedup from pipelining equal to the number of pipeline stages?
  • What factors prevent pipelines from achieving the ideal speedup?
  • What characteristics of the RISC-V instruction set suggest that it was designed for pipelined execution?
  • What sort of dangers or risks arise in the processor because of pipeline hazards?
  • What are structural hazards, and how can they be eliminated?
  • What are data hazards, and how do they arise?
  • What are control hazards, and what kind of instructions are in the pipeline when they occur?
  • It is feasible to rely on the compiler to generate code without any hazards?
  • What does it mean to stall the pipeline?
  • Can all hazards be dealt with correctly by stalling?
  • What is the key idea behind forwarding?
  • Does forwarding eliminate all stalls on data hazards?
  • What role can prediction play in addressing control hazards?
• Section 4.7 - Pipelined Datapath and Control
  • What are the five stages in the pipelined datapath in our text?
  • What actions are performed in each stage?
  • What hardware resources of the datapath are associated with each stage?
  • Can components of the datapath be used by multiple stages in the same cycle?
  • What hardware resources must be added to the datapath in order to pipeline the execution?
  • Are pipeline registers part of the visible architectural state of a processor?
  • What are the naming conventions for the pipeline registers? (Which stages does the EX/MEM register separate, for example?)
  • In general terms, what information must be stored in each pipeline register?
  • In Fig. 4.38 (and many others), what is the significance of highlighting (in blue) half of a register or memory used in a given stage?
  • What kind of diagrams are used to depict the step-by-step actions of instruction execution in a pipeline?
  • Given a sequence of RISC-V instructions and the associated multiple-clock-cycle pipeline diagram (as in Figure 4.45), can you determine when data hazards occur? Can you describe how those hazards might be resolved?
  • Are all the control signals used in the single-cycle datapath also used in the pipelined datapath?
  • Why are there no write signals for the PC or the pipeline registers?
  • What control signals are required in each stage of the pipeline?
  • Can control signals be generated before the cycle when they are needed?
  • In the RISC-V pipeline, what happens if a register is read and written in the same clock cycle?
  • What does the notation “EX/MEM.RegisterRd” refer to?
  • What other values can be referred to using similar notation?
  • Using this notation, how are data hazards identified?
  • What is the significance of the blue lines in Figure 4.53?

Exam Preparation LLM Prompts

Large Language Models (LLM) like ChatGPT can be very useful in helping you prepare for the exam. The following examples are prompts that you could try to help generate practice problems for exam preparation.

System Prompt:

I am an undergraduate student at BYU in Electrical and Computer Engineering and taking ECEN 423 - Computer Organization.
This class uses the textbook 'Computer Organization and Design RISC-V Edition'.
I have an upcoming exam that covers chapter 3 on computer arithmetic and sections 4.6-4.16 on pipelining.
Please generate a set of practice exam multiple choice questions based on the following study questions.

(paste the questions listed above)