ECEn 423
Tutorials Resources TA and Lab Hours ECEN 423 Coding Standards AI Class Policy
Labs
Lab 1 - SystemVerilog Review Lab 2 - ALU Lab 3 - Register File Lab 4 - RISC-V Simulator Lab 5 - RISC-V Datapath Lab 6 - RISC-V Control Lab 7 - RISC-V I/O System Lab 8 - Pipelined RISC-V Lab 9 - RISC-V Forwarding Lab 10 - VGA Download Lab 11 - Final Processor Lab 12 - Final Project

Resources

  • Details about the Basys3 board
  • SystemVerilog Resources
  • RISC-V Resources
  • Digital Lab Queue
  • Basys3 I/O System
  • Exam Review Questions

Last Modified: 2026-02-20 02:10:15 +0000