Exam Format

• The exam will be held in the testing center.
• Material covered: Chapters 1, 2, and 4 (up to section 4.5).
• 25 multiple choice questions
• Closed book
• Access to testing center calculator
• You may write on the exam
• No time limit on the exam (the average student takes about 1 hour to complete the exam)

The following tables and figures will be given on the exam:

• Figure 4.19
• Detailed description of RISC-V instruction formats

Exam Preparation Suggestions

• Review the ‘Exam Review Questions’ listed below
  • These are not questions that will be put on the exam but questions that suggest what areas we discussed you should review. No question will be given on the exam that doesn’t relate to at least one of the questions below.
• Review homework questions
• Review textbook (see review questions on areas of the textbook to review)
  • Some questions on the textbook may be given that are not explicitly covered in class.
• Review in class quizzes

Exam Review Questions

Chapter 1

• Section 1.1 - Introduction
  • How does a mebibyte differ from a megabyte? (see Figure 1.1)
  • What are the distinguishing characteristics of computing in the “Post-PC era”?
  • What are the different type of computers and what are their characteristics (see Figure 1.2)?
• Section 1.2 - Seven Great Ideas in Computer Architecture
  • What is “Moore’s Law”?
• Section 1.3 - Below Your Program
  • What advantages do high-level languages offer, relative to programming in assembly language or machine language?
  • What is the purpose of the compiler and assembler?
  • What steps are involved in the translation of a program from a high-level language to a form the hardware can understand?
  • What key roles does systems software play in modern computer systems?
• Section 1.4 - Under the Covers
  • On typical systems, how does a processor change what is visible on a graphics display?
  • What kinds of memory or storage technologies are said to be volatile?
• Section 1.5 - Technologies for Building Processors and Memory
  • What are key steps in the manufacturing of integrated circuits?
• Section 1.6 - Performance
  • How do you measure computer performance?
  • How are performance and execution time related?
  • How do you compare performance between different computers?
  • What precisely does it mean if “computer X is n times faster than computer Y”?
  • What is “CPI” and how does it relate to performance?
• Section 1.7 - The Power Wall
  • What was the “power wall” that computer designers ran into, and how did their designs change as a result?
• Section 1.9 - Real Stuff: Benchmarking the Intel Core i7
  • Why is the geometric mean used for performance comparisons and how do you compute it?
• Section 1.11 - Fallacies and Pitfiles
  • What is Amdahl’s Law, and why is it useful?

Chapter 2

• Section 2.1 - Introduction
  • What is the instruction set of a computer?
  • What is the stored-program concept, and why is it “the secret of computing”?
• Section 2.2 - Instructions: Langauge of the Computer
  • How are instructions typically represented for human use?
  • In RISC-V, how does x0 differ from other registers?
• Section 2.3 - Operands of the Computer Hardware
  • In RISC-V, how is a memory address determined for a load or store?
  • What is the difference in address values for adjacent elements of an array of words?
  • What does it mean for data elements to be aligned in memory?
  • What is the difference between little endian and big endian? What is the convention for RISC-V?
  • How do bytes get stored in memory using the sw instruction.
  • Does RISC-V have alignment restrictions?
  • Why did the RISC-V designers not include a subi instruction?
  • What does it mean for a program to spill registers?
  • What are the advantages of arithmetic instructions that have an immediate operand?
  • In these instructions, where is the constant immediate value actually stored?
  • By convention, is bit 0 the least or most significant bit in a word or word?
• Section 2.4 - Signed and Unsigned Numbers
  • What is sign extension?
• Section 2.5 - Representing Instructions in the Computer
  • In what form are instructions when they are executed by the hardware?
  • What fields exist in RISC-V instructions?
  • Which fields are always in the same place?
  • How does the hardware know the format of any given instruction?
  • What are the four addressing modes in the RISC-V ISA?
• Section 2.6 - Logical Operations
  • How does the sra instruction differ from the srl instruction?
  • How can logical operations be used to read and write arbitrary bit fields within a word?
• Section 2.7 - Instructions for Making Decisions
  • How are conditional branches in RISC-V typically used to implement if statements and loops?
  • What is a basic block?
  • How does the blt instruction differ from the bltu instruction?
• Section 2.8 - Supporting Procedures in Computer Hardware
  • What is the stack, and how is it used to support procedures?
  • What is the heap, and how is it used by C programs?
  • What is the difference between the jal and jalr instructions?
  • How are parameter values passed to functions, and how do functions return values?
  • What instruction is used to call a function, and how is the return address saved?
  • What instruction is used to return from a function?
  • How is the stack used to support procedures, and under what conditions is a stack frame allocated?
  • How are procedures implemented in RISC-V code?
• Section 2.9 - Communicating with People
  • How does the ‘lb’ instruction differ from the ‘lbu’ instruction?
  • What memory-access instructions would you expect to see in a program that manipulates ASCII strings?
• Section 2.10 - RISC-V ADdressing for Wide Immediates and Addresses
  • What does the lui instruction do?
  • What is PC-relative addressing, and which RISC-V instructions use it?
  • Why did RISC-V architects choose to encode the distance from the branch instruction to the branch target in halfwords (rather than bytes or words)?
  • What does the auipc instruction do, and how might it be used?
• Section 2.12 - Translating and Starting a Program
  • What is the difference between assembly language and machine language?
  • What are the key steps in translating and running a C program, and what system tools are used in the process?
  • How likely is it that a human programmer can create more efficient code in assembly language than the compiler can generate from C code?
  • What is a pseudoinstruction, and what examples are given in our text?
• Section 2.14 - Arrays vs. Pointers
  • Why can C code that uses pointers sometimes be more efficient than a version that uses arrays and array indices?
• Section 2.20 - Real Stuff: The rest of the RISC-V Instruction Set
  • What does the slt instruction do, and what other set instructions exist?

Chapter 4 - part A

• Section 4.1 - Introduction
  • What is the Program Counter?
  • What subset of RISC-V instructions are supported in the implementation presented by our text?
  • What important instructions are not included in their design?
  • What are the consequences in the design of implementing just a small subset of instructions?
  • In Fig. 4.2, which parts of the datapath are combinational elements, and which are state elements?
  • What role does the control unit play in the execution of instructions?
  • What role does each of the 3 multiplexors play in the datapath shown in Figure 4.2?
• Section 4.2 - Logic Design Conventions
  • What role does the clock play in the operation of the datapath?
  • What is a clocking methodology?
  • If a design uses positive edge-triggered state elements, what happens only on rising clock edges?
  • What inputs does every state element have?
  • In Figure 4.3, what determines the length of a clock cycle?
• Section 4.3 - Building a Datapath
  • Why isn’t the ALU used to increment the PC?
  • For the RISC-V datapath, how many ports must the register file have? Why?
  • How is it possible for the register file to read and write the same register in the same clock cycle?
  • If a read and write occur to the same register in the same clock cycle, what value does the read return?
  • What are the consequences of the register file having a write control signal but no read control signal?
  • Why does the data memory require both read and write signals, unlike the register file?
  • What is the 32-bit input to the Imm Gen unit?
  • What does the Imm Gen unit do?
  • How does the Imm Gen unit know how the immediate value is encoded?
  • What input(s) must be provided to the register file to read or write a given register?
  • In the RISC-V datapath, what are the two possible values that could be used to update the PC at the end of each cycle?
  • Why isn’t the ALU used to compute the branch target address for branch instructions?
  • What is the purpose of the “Zero” output of the ALU?
  • Why does the branch offset have to be shifted left by one bit, and what hardware is required to do it?
  • What are the two possible values that could appear on the lower input to the ALU in each cycle?
• Section 4.4 - A simple Implementation Scheme
  • What processing steps do most RISC-V instructions have in common?
  • In figures throughout Chapter 4, what is the significance of signals drawn and labeled in blue?
  • What do each of the 7 control signals do that are generated by the Control unit? (See Fig. 4.20)
  • What control signal in Fig. 4.17 is generated using multiple levels of decoding?
  • What is the main motivation for using multiple levels of control logic?
  • How many bits wide is the ALUOp value generated by the first level of control logic?
  • What additional inputs are used in the second level of control logic?
  • How many different functions can the ALU perform in the simple implementation in the text?
  • How many bits wide is the input to the ALU in the simple implementation in the text?
  • What control signals does the datapath require that cannot be generated using only the 7 opcode bits?
  • For each instruction, can you specify the value of each of the control signals?
  • What are the two possible values that could be used to update a register in the register file at the end of each cycle?