ECEn 323
Tutorials Resources TA Hours ECEN 323 Coding Standards
Labs
Lab 1 - SystemVerilog Review Lab 2 - ALU Lab 3 - Register File Lab 4 - RISC-V Simulator Lab 5 - RISC-V Datapath Lab 6 - RISC-V Control Lab 7 - RISC-V I/O System Lab 8 - Pipelined RISC-V Lab 9 - RISC-V Forwarding Lab 10 - VGA Download Lab 11 - Final Processor Lab 12 - Final Project

SystemVerilog Resources

This page provides links to resources that will help you brush up on your SystemVerilog design skills.

  • ECEN 220 Lecture Slides
    • Structural SystemVerilog
    • Implementing Hierarchy
    • Dataflow SystemVerilog
    • Implementing Registers
    • Behavioral Combinational
    • Implementing Memory
    • Implementing FSMs
  • Online Verilog Reference Guide - Southerland HDL

Last Modified: 2025-01-01 00:09:11 +0000