Vivado Command Line Synthesis Tutorial

The Vivado design suite has a professional synthesis tool that will synthesize your SystemVerilog into a format useable by the FPGA. This synthesis tool is used by professional engineers to create large, complex digital designs for FPGAs. Your ability to use synthesis tools effectively is key to successfully designing digital circuits. This tutorial will guide you through how to synthesize a simple circuit using the command line. This tutorial will demonstrate this process using the binary adder design from Lab 2.

XDC Files

When synthesizing a SystemVerilog design to a specific FPGA, you need to provide a mapping between the top-level input and output ports and the specific pins on the FPGA. For the binary adder design we are using for this tutorial, you need to indicate the pins on the FPGA for each of the input switches and indicate the pins on the FPGA for each of the LEDs. This mapping is described in a ‘Xilinx Design Constraints’ file or .xdc file. An .xdc file has been created for you for this tutorial. In future laboratory assignments you will need to create your own .xdc file - a tutorial has been created to help you with this process.

Vivado Tool Shell

To perform synthesis, you will need to run the Vivado tool shell. This tool can be run by executing the following command in the terminal using the -mode tcl option:

vivado -mode tcl -log synthesis.log

The -log synthesis.log flag will log all the Vivado tool shell output to the synthesis.log file.

It is necessary for you to log this output so you can carefully review it later.

The following output will be displayed and you will be in the Vivado tool shell (noted by the Vivado% prompt):

****** Vivado v2024.1 (64-bit)
  **** SW Build 5076996 on Wed May 22 18:36:09 MDT 2024
  **** IP Build 5075265 on Wed May 22 21:45:21 MDT 2024
  **** SharedData Build 5076995 on Wed May 22 18:29:18 MDT 2024
  **** Start of session at: Tue Dec 31 11:17:55 2024
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.

Vivado%

At this point you can enter various Tcl commands into the shell to perform the synthesis process. Specific commands that you need to run will be described below. The tutorial will first discuss which commands to execute for synthesis interactively and then describe a how to create a script and run it in batch mode.

Read Files

The first step in the synthesis process is to ‘read’ your files into the synthesis tool. The read_verilog command is used to read in your SystemVerilog files (note the use of the -sv option to indicate that the file is a SystemVerilog file). The following example demonstrates reading the binary_adder.sv file into the synthesis tool:

Vivado% read_verilog -sv binary_adder.sv

This command acts much like the xvlog command you used for simulation in that it ‘analyzes’ the SystemVerilog file. If there are any errors in your SystemVerilog file you will see the error messages and will not be able to proceed to synthesis. It is best to thoroughly simulate your files first and resolve all errors before proceeding to this synthesis step.

After all of the SystemVerilog files have been read into the synthesis tool, you need to read in the XDC file using the read_xdc Tcl command. The following command demonstrates reading the binary_adder.xdc file into the synthesis tool:

Vivado% read_xdc binary_adder.xdc

At this point, all the necessary files have been read into the synthesis tool and you are ready to proceed to the actual synthesis step.

Synthesis Command

The synthesis tool will carefully analyze your design and create a netlist that maps your logic to specific logic resources on the FPGA. This tool will generate a lot of messages during the synthesis process that will be necessary to review. It will generate warnings, information messages, and errors. The tool allows you to change the severity of messages as needed so you can safely ignore some messages and focus on others. It is necessary to change the default severity levels of some messages that the synthesis tool generates (some are less important to us while others are more important to us.) A Tcl script has been added to the startercode that will adjust the message severity levels for you. You can execute this script by running the source command as follows:

source ../resources/messages.tcl

With your files properly loaded, and the message severity set properly you are ready to run the actual synthesis command. The following command demonstrates running the synthesis command:

synth_design -top binary_adder -part xc7a35tcpg236-1 -verbose

The flags for the synth_design command are as follows:

  • -top specifies the top-level module of your design
  • -part specifies the FPGA part number you are targeting. The part on the Basys3 board is xc7a35tcpg236-1. You will be using this same part for all the labs in this class.
  • -verbose specifies that you want verbose output from the synthesis tool

This command will take some time to execute and will generate a lot of output. The output is important to review and any errors or warnings should be addressed before proceeding to the next step (you shouldn’t have any synthesis warnings at this point as the ‘xdc’ and ‘sv’ files were created for you). Review the synthesis.log file to see if you have any warnings or errors from the synthesis tool.

Create Checkpoint File

If your synthesis was successful, the last step is to save the results of the synthesis in a “design checkpoint” or .dcp file. This checkpoint file will be used for the final implementation step. The following command demonstrates writing the checkpoint file:

write_checkpoint -force binary_adder_synth.dcp

This creates a checkpoint file named binary_adder_synth.dcp that you can use to proceed to the implementation step.

Batch Mode

The above example demonstrates how to perform synthesis interactively. Like simulation, it is more convenient to create a ‘.tcl’ script that runs all of these commands at once in batch mode. Create a file named synth_adder.tcl that contains all the commands described above. You can complete the full synthesis process by running the following command:

vivado -mode batch -source synth_adder.tcl -log synth_adder.log -nojournal -notrace

The flags for flags for this command are as follows:

  • -mode batch - specifies that the Vivado tool should run in batch mode
  • -source synth_adder.tcl - specifies the Tcl script that contains the synthesis commands
  • -log synth_adder.log - specifies that you want to log the output of the synthesis tool to the synth_adder.log file
  • -nojournal - specifies that you do not want to create a journal file
  • -notrace - specifies that you do not want to create a trace file

As with the simulation commands, logic synthesis will generate a lot of temporary files that need to be ignored and cleaned. Run your synthesis script to make sure that the binary_adder example properly synthesizes.