Creating XDC Constraint Filess

A Xilinx Design Constraints file or .xdc file is needed to interface between your SystemVerilog modules and the Basys3 board. An XDC file is required to generate configuration bit file. The XDC file performs the following important functions:

• Maps the inputs and outputs of your module to the physical pins on the FPGA and sets important properties for the pins, such as the voltage standard.
• Specifies important parameters for the synthesis and implementation tools
• Defines input clocks for synchronous designs. Each of these functions will be described below with examples.

Mapping Pins to Ports

Most of the commands in a constraint file assign pin locations to top-level ports. For every pin you use, you will need the following line of code:

set_property -dict { PACKAGE_PIN <PIN_NAME> IOSTANDARD LVCMOS33 } [get_ports { <PORT_NAME> }];

The ‘PORT_NAME’ is the name of the top-level port in your SystemVerilog module that you want to connect to the pin. The following example command demonstrates assigning the A port of a top-level Verilog design to pin W16 on the FPGA.

set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { A }];

set_property is a Tcl command is used to attach properties to design elements (you can type help set_property in the Tcl console to learn more about this command). Two options are being passed to this command, -dict and get_ports.

-dict This argument provides a dictionary, a set of name/value property pairs, all in a single command. In this example, two pairs are being added to the port:

• PACKAGE_PIN indicates which pin the signal should be assigned to. In this example, the signal is attached to the W16 pin (this pin is attached to switch 2 on the FPGA).
• IOSTANDARD configures the pin to operate a specific voltage standard. In this case, we are configuring the pin as LVCMOS33 which translates to Low-Voltage CMOS using 3.3V supply. You must assign values to these two properties for all pins you use on the FPGA.

get_ports

This argument actually executes the command get_ports{A}, meaning find the top-level port named A. The result of this command is used as the second argument of the set_property command, allowing it to connect the pins from dict to the ports in get_ports.

You will need to make sure that the <PIN_NAME> and <PORT_NAME> match for every top-level port.

Synthesis and Implementation Properties

Design properties and constraints can be added to the .xdc file to specify properties that are unique to your design or board. The following to commands should be added to the .xdc file of each of your designs.

# Sets the configuration voltage to 3.3V. This is dictated by the Basys3 board design.
set_property CONFIG_VOLTAGE 3.3 [current_design]
# Sets the configuration bank voltage standard. In this case, it is tied to the FPGA's VCCO voltage
set_property CFGBVS VCCO [current_design]
## Compression is used to reduce the size of the bitstream file
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

Input Clock Specification

The input clock is a special signal that is used to synchronize the operation of the FPGA. In addition to the conventional pin assignment for the clock, you need to identify this signal as a clock and specify the clock frequency. The following example demonstrates how to specify the clock signal clk on pin W5 with a frequency of 10 MHz.

set_property -dict { PACKAGE_PIN W5    IOSTANDARD LVCMOS33 } [get_ports { clk }];
create_clock -period 10.00 [get_ports { clk }];

Master XDC file

Creating XDC files is tedious and repetitive. To make things easier, you’re provided with a master XDC file that contains all the XDC constraints for each pin on the Basys 3 that you will use in these labs.

Rather than typing in all of the constraints, you can copy this file for each lab and modify it as needed. You need to perform these two steps to modify the master XDC file for your top-level design:

1. Uncomment the lines in the XDC file that correspond to pins that your design uses. Do this by removing the “#” character at the beginning of the line.
2. Modify the port names to match the top-level input and output ports of your design. Do this by changing the values inside the curly braces “{}” of the “get_ports { }” portion of the command.
3. In some labs, the top level port names will match what is already in the XDC file (“sw[0]” for example) and so you won’t have to change them. In other labs, the top level port names will not match what is already in the XDC file and you will have to change them in the XDC file.