Error Messages

Table of Contents

This page provides a summary of common warning and error messages that you may encounter in your designs. An example and a description of the message is provided for each error message. Suggestions for resolving the message are also provided. The message ID is a unique identifier for the error message. Common message IDs are linked below.

WARNING: [Synth 8-3332] Sequential element (tx/FSM_onehot_cs_reg[6]) is unused and will be removed from module tx_top.

Error Messages

Common 17-55

CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/home/wirthlin/ee320/320-labs-wirthlin/lab04/arithmetic_top.xdc:33]

This message occurs because you have a ‘set_property’ command in an .xdc file (or a .tcl file) that references an object that does not exist. This most often occurs when you have an entry in your .xdc file that does not match any ports in your design. If this is the case you will also see a Vivado 12-584 message.

DRC NSTD-1

ERROR: [DRC NSTD-1] Unspecified I/O Standard: 1 out of 26 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT',
instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or 
connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components 
to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a 
bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with 
unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks 
NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl 
file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: sw[15].

This message indicates that at least one port has an undefined IOSTANDARD entry in the .xdc file. The port that has the problem is at the end of the message (see Problem ports: sw[15]) at the end of this message. To fix this problem, go back to your .xdc file and make sure there is an entry for the missing port. This message usually comes in conjunction with the DRC UCIO-1 message.

DRC UCIO-1

ERROR: [DRC UCIO-1] Unconstrained Logical Port: 1 out of 26 logical ports have no user assigned specific location
constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting
performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected.
To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical
ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations 
(not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the 
Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a 
pre-hook for write_bitstream step for the implementation run.  Problem ports: sw[15].

This message indicates that at least one port has not been defined in the .xdc file. The port that has the problem is at the end of the message (see Problem ports: sw[15]). To fix this problem, go back to your .xdc file and make sure there is an entry for the missing port. This message usually comes in conjunction with the DRC NSTD-1 message.

Synth 8-659

ERROR: [Synth 8-659] type mismatch in input port connection: bit [7:0]A vs. bit B[7:0] [/home/wirthlin/ee320/320-labs-wirthlin/lab04/arithmetic_top.sv:24]

This is a message that occurs during synthesis when you have provided incorrect indices for a port or signal. To fix this, move the index range before the signal or port name. This is similar to the VRFC 10-395 message that you may get when trying to simulate a SystemVerilog file with the same problem.

Synth 8-3332

WARNING: [Synth 8-3332] Sequential element (tx/FSM_onehot_cs_reg[6]) is unused and will be removed from module tx_top.

This message indicates that a register in your design is not being used and will be removed from the design. In most cases, this is a problem and you should investigate why the register is not being used.

There are a few cases when this warning is acceptable. Sometimes the synthesis tool will synthesize an extra state in a state machine named ‘iState’. Later when the synthesis tool optimizes the state machine, it will remove the unused state. If the state machine is encoded with a one-hot encoding style, the register bit associated with the state will be removed. Search for ‘iState’ in the synthesis log and see if this state has been inferred for your state machine.

Vivado 12-584

WARNING: [Vivado 12-584] No ports matched 'anode[2]'. [/home/wirthlin/ee320/320-labs-wirthlin/lab04/arithmetic_top.xdc:33]

This message indicates that there is a port in the .xdc file that does not match any ports in the design. The port that has a problem is andode[2] in this case. To fix this problem, remove or comment the line in the .xdc file that includes the offending port. This warning usually comes in conjunction with the Common 17-55 message.

VRFC 10-395

ERROR: [VRFC 10-395] cannot assign an unpacked type to a packed type [/home/wirthlin/ee320/320-labs-wirthlin/lab04/arithmetic_top.sv:24]

This means that you have put the index range after the signal or port name rather than before it. To fix this, move the index range before the signal or port name. This is similar to the Synth 8-659 message that you will get when trying to synthesize a SystemVerilog file with the same problem.