Correct Examples

Table of Contents

G1: Plain ASCII Text

Rule: Code must be plain ASCII with no non-printable characters.

Correct Example:

(You can open this file in any basic text editor. There are no hidden or non-ASCII characters.)
Everything here is plain ASCII text.
No strange symbols or control characters are present.

See Incorrect Example

G2, G3, G4, G5, G6: File Header

Rule: Every code file submitted must have a header comment block containing:

  1. An opening/closing line of characters.
  2. Filename.
  3. Author.
  4. Description (at least one complete sentence).

Correct Example (SystemVerilog file header):

/***************************************************************************
* 
* Filename: traffic_light.sv
*
* Author: John Doe
* Description: This module controls traffic lights by cycling through states
*              for main and side roads using an internal clock divider.
*
****************************************************************************/

module traffic_light (...);
    // ...
endmodule

See Incorrect Example

G7: White Space

Rule: Sufficient white space must be used to make the file easy to read.

Correct Example:

/***************************************************************************
* 
* Filename: my_module.sv
*
* Author: Jane Doe
* Description: This module demonstrates correct use of white space.
*
****************************************************************************/

module my_module(
    input logic clk,
    input logic rst
);
    localparam int MAX_COUNT = 10; // Maximum count value
    
    // Internal signals
    logic count_done;
    logic [3:0] counter;
    
    
    // ------------------------------------------------
    // Timer logic
    // ------------------------------------------------
    
    // Increase count
    always_ff @(posedge clk) begin : counter_ff
        if (rst) begin 
            count <= 0;
        end else begin
            count <= count + 1;
        end
    end
     
    // Assert done if count reaches 10
    always_comb begin : done_logic
        if (count == 10) begin
            done = 1;
        end else begin
            done = 0;
        end
    end
    
    // Output logic
    assign output_signal = done && count;
    assign another_signal = count || done;
    
    
    // ------------------------------------------------
    // State machine logic
    // ------------------------------------------------
    
    // State machine logic
    always_ff @(posedge clk) begin : state_ff
        if (rst) begin
            state <= IDLE;
        end else begin
            state <= next_state;
        end
    end
    
    // ...
endmodule

See Incorrect Example

G8: Line Length

Rule: No lines longer than 90 columns. Split long lines as needed.

Correct Example:

// Demonstrates splitting a long statement onto multiple lines to keep
// each line under ~90 characters.
assign longSignalName = someCondition && anotherCondition &&
                        yetAnotherCondition && finalCondition;

// Instantiation of a module with parameters
some_module instanceName(
    .clk(clk),          // Clock input
    .rst(rst),          // Reset input
    .input1(input1),    // Input 1
    .input2(input2),    // Input 2
    .output1(output1),  // Output 1
    .output2(output2),  // Output 2
    .config(config),    // Configuration input
    .enable(enable)     // Enable signal
);

assign result = (timerDone && bitCounter) || (dataValid && parityCheck) 
                || (addressMatch && readEnable) || (writeEnable && bufferFull)
                && (dataReady || dataError);

See Incorrect Example

G9: Indentation

Rule: Indentation must clearly indicate code structure.

Correct Example:

module indentation_example(
    input logic clk,
    input logic rst
);

    // Indented in module, then always_ff, then if-else
    always_ff @(posedge clk) begin
        if (rst) begin
            // Reset logic
        end else begin
            // Normal operation
        end
    end

endmodule

See Incorrect Example

S1 and S2: Files

Rule: A new .sv file per SystemVerilog module, and the filename must match the module name.

Correct Example:

File name: timer_controller.sv
Module name: timer_controller

(One module in timer_controller.sv with the same name.)

File name: clock_divider.sv
Module name: clock_divider

(Separate file for each module.)

See Incorrect Example

S6, S7, S8: Signal Types

Rule:

  • Inputs must be declared as input logic.
  • Outputs must be declared as output logic.
  • Internal signals must be declared as logic.
  • Do not use reg, wire, var, bit, int, genvar, etc., in the module.

Correct Example:

module correct_signal_types #(
    parameter WIDTH = 8
) (
    input logic clk,
    input logic rst,
    output logic validOutput
);
    // Internal Constants
    localparam MAX_COUNT = 255;
    
    // Internal Signals
    logic internalSignal;
    
    // Internal State Machine
    typedef enum logic [1:0] {
        IDLE, RUNNING, DONE
    } state_t;
    state_t currentState, nextState;
    
    // ...
endmodule

See Incorrect Example

S10: Descriptive Signal Names

Rule: Use descriptive names or add comments if the name alone is unclear.

Correct Example:

logic clearTimer;  // Clears the main timer register
logic nextState;   // Next state for the FSM

// Five input `and` gate for ... (Descriptive comment for each non-descriptive signal name)
logic a5;

See Incorrect Example

S11: Active-Low Signals

Rule: Use _n suffix for active-low signals.

Correct Example:

input logic write_n;  // Active-low write

See Incorrect Example

S12: No Initializers in Declarations

Rule: Do not write logic signal = 0;; instead, reset signals in an always_ff block.

Correct Example:

logic next_state;

always_ff @(posedge clk) begin
    if (rst) begin
        next_state <= 0;  // Proper reset usage
    end else begin
        next_state <= 1;
    end
end

See Incorrect Example

S13: Comments Before always_ff / always_comb

Rule: Each always_ff and always_comb block must be preceded by a comment describing its function.

Correct Example:

// State register for the FSM
always_ff @(posedge clk) begin
    // ...
end

// Next state logic
always_comb begin
    // ...
end

See Incorrect Example

S14: Comments Before Module Instantiation

Rule: Each module instantiation must have a comment explaining its purpose.

Correct Example:

// Instantiates the clock divider module for generating slow_clk
clock_divider div_inst(
    .clk_in(clk),
    .clk_out(slow_clk)
);

// Instantiates the main module with input and output signals for some purpose...
some_module instanceName(
    .clk(clk),
    .rst(rst),
    .input1(input1),
    .output1(output1)
);

See Incorrect Example

S16: Assignment Operators in always_ff / always_comb

Rule: Use <= in always_ff, and = in always_comb or assign.

Correct Example:

always_ff @(posedge clk) begin
    regA <= regB; // correct for sequential
end

always_comb begin
    result = opA + opB; // correct for combinational
end

See Incorrect Example

S17: Default Assignments in always_comb

Rule: Every signal in always_comb must have a defined value.

Correct Example:

always_comb begin
    // Defaults
    next_state = current_state;
    
    // ...
end

See Incorrect Example

S18: Register Reset

Rule: Each always_ff must have a reset, clr, or load to set registers to known values.

Correct Example:

always_ff @(posedge clk) begin
    if (rst) begin
        counter <= 0; // known value
    end else begin
        counter <= counter + 1;
    end
end

See Incorrect Example

S19: One Register per always_ff

Rule: Don’t assign multiple unrelated registers in the same always_ff.

Correct Example:

// State register
always_ff @(posedge clk) begin
    if (rst) begin
        state <= 0;
    end else begin
        state <= next_state;
    end
end

// Timer register
always_ff @(posedge clk) begin
    if (rst) begin
        timer_reg <= 0;
    end else begin
        timer_reg <= timer_reg + 1;
    end
end

See Incorrect Example

S20: Proper Reset Structure

Rule:

  • The if (rst) condition must always appear first in every always_ff block.
  • Never combine the initial reset condition with other signals using ||.
  • Handle secondary clear signals in the else branch after checking reset.
  • Place all subsequent sequential logic inside the else branch.

Correct Example:

// Sequential logic with proper reset structure
always_ff @(posedge clk) begin
    if (rst) begin
        // Reset branch: All registers are set to known values.
        data_reg <= 0;
    end else begin
        // Handle secondary clear signal after global reset has been checked.
        if (clrBit) begin
            data_reg <= 0;
        end else begin
            data_reg <= data_in;
        end
    end
end

// Timer register with proper reset structure (if-else)
// The || is OK, as long as it's not combined with the rst.
always_ff @ (posedge clk) begin : always_block_missing_rst
    if (rst) begin
        timer <= 0;
    end else begin
        if (clrTimer || timerDone) begin
            timer <= 0;
        end else begin
            timer <= timer + 1; 
        end
    end
end

// Combinational logic does not include reset conditions.
// Instead, it uses default assignments to prevent latches.
always_comb begin
    // Default assignments for all outputs.
    next_state = current_state;
    output_signal = 0;

    // Combinational logic based on the current state.
    case (current_state)
        STATE_IDLE: next_state = STATE_RUN;
        STATE_RUN:  next_state = STATE_IDLE;
        default:    next_state = STATE_IDLE; // Optional default as we have a default above.
    endcase
end

See Incorrect Example

S21: Grouping Code by Submodules

Rule: Separate different functional logic sections with comments.

Correct Example:

// ------------------------------------------------
// Timer logic
// ------------------------------------------------

// Timer register
always_ff @(posedge clk) begin
    // ...
end

assign timer_done...


// ------------------------------------------------
// State machine logic
// ------------------------------------------------

// State register
always_ff @(posedge clk) begin
    // ...
end

// Next state logic
always_comb begin
    // ...
end

See Incorrect Example

S22: Local Signal Declarations

Rule: Signals declared immediately after module ports.

Correct Example:

module example_module(
    input logic clk,
    input logic rst
);
    // Internal Constants
    localparam MAX_COUNT = 255;
    
    // Internal Signals
    logic internalSignal;
    logic count_done;
    logic [3:0] counter; // Timer for ... (describe ambiguous signals)
    
    // Internal State Machine
    typedef enum logic [1:0] {
        IDLE, RUNNING, DONE
    } state_t;
    state_t currentState, nextState;

    // ...
endmodule

See Incorrect Example

S23: Naming Conventions

Rule:

  • Use PascalCase or snake_case for module names.
  • Use camelCase or snake_case for signals.
  • Use UPPER_SNAKE_CASE for constants.
  • Keep naming conventions consistent.

Correct Example:

module traffic_light_controller(
    input logic clk,
    input logic rst
);
    localparam MAX_COUNT = 10;
    logic clrBit, clrTimer;
    logic [3:0] timerCount; // Timer for the traffic light
    
    // ...
endmodule

See Incorrect Example