Incorrect Examples

Table of Contents

G1: Plain ASCII Text

Rule: Code must be plain ASCII with no non-printable characters.

Incorrect Example:

(There are strange characters here: ☺☻♥)  <-- Non-ASCII
These might show up as boxes or unknown symbols in an editor.

See Correct Example

G2, G3, G4, G5, G6: File Header

Rule: Every code file submitted must have a header comment block containing:

  1. An opening/closing line of characters.
  2. Filename.
  3. Author.
  4. Description (at least one complete sentence).

Incorrect Example (No header, or incorrect or missing required fields):

// Header is missing (This file has no formal header: it's missing filename, author, and description)
module no_header_module(...);
    // ...
endmodule

OR

/* Filename: debouncer sv module
* Author: myGithubOrNetID
* Description: debounces stuff. Uses timer to stop bouncing from logging.*/

See Correct Example

G7: White Space

Rule: Sufficient white space must be used to make the file easy to read.

Incorrect Example:

/***************************************************************************
* 
* Filename: my_module.sv
*
* Author: Jane Doe
* Description: This module demonstrates incorrect use of white space.
*
****************************************************************************/

module my_module(input logic clk,input logic rst);
    localparam int MAX_COUNT = 10; // Maximum count value
    // Internal signals
    logic count_done;
    logic [3:0] counter;
    // ------------------------------------------------
    // Timer logic
    // ------------------------------------------------    
    // Increase count
    always_ff @(posedge clk) : counter_ff begin if (rst) begin count<=0; end else begin count<=count+1; end end 
    // Assert done if count reaches 10
    always_comb begin : done_logic
        if (count==10) begin
            done=1;
        end else begin
            done=0;
        end
    end
    // Output logic
    assign output_signal = done&&count;
    assign another_signal = count||done;
    // ------------------------------------------------
    // State machine logic
    // ------------------------------------------------
    // State machine logic
    always_ff @(posedge clk) begin : state_ff
        if (rst) begin
            state <= IDLE;
        end else begin
            state <= next_state;
        end
    end
    // ...
endmodule

(Everything is crammed together with no spacing.)

See Correct Example

G8: Line Length

Rule: No lines longer than 90 columns. Split long lines as needed.

Incorrect Example:

some_module instanceName(.clk(clk), .rst(rst), .input1(input1), .input2(input2), .output1(output1), .output2(output2), .config(config), .enable(enable));
assign result = (timerDone && bitCounter) || (dataValid && parityCheck) || (addressMatch && readEnable) || (writeEnable && bufferFull) && (dataReady || dataError);

See Correct Example

G9: Indentation

Rule: Indentation must clearly indicate code structure.

Incorrect Example:

module bad_indentation_example(
input logic clk,
input logic rst
);

// Nothing indented
always_ff @(posedge clk) begin
if(rst) begin
// ...
end else begin
// ...
end
end

endmodule

(No indentation to show hierarchy or code structure.)

See Correct Example

S1 and S2: Files

Rule: A new .sv file per SystemVerilog module, and the filename must match the module name.

Incorrect Example:

File name: timer_and_clock.sv
Module name: timer_controller
Module name: clock_divider

(Multiple modules in one file. Also, the file name doesn't match either module name.)

See Correct Example

S6, S7, S8: Signal Types

Rule:

  • Inputs must be declared as input logic.
  • Outputs must be declared as output logic.
  • Internal signals must be declared as logic.
  • Do not use reg, wire, var, bit, int, genvar, etc., in the module.

Incorrect Example:

module incorrect_signal_types(
    input bit clk,  // 'bit' not allowed
    input logic wire rst, // 'logic wire' combination not allowed
    output var done // 'var' not allowed
);

    reg internalWire;     // 'reg' is not allowed
    wire something_else;  // 'wire' also not allowed

endmodule

See Correct Example

S10: Descriptive Signal Names

Rule: Use descriptive names or add comments if the name alone is unclear.

Incorrect Example:

logic n5;       // Not descriptive, no comment
logic xyz;      // Also unclear
logic count;    // 'count' is too generic, counts for what?

See Correct Example

S11: Active-Low Signals

Rule: Use _n suffix for active-low signals.

Incorrect Example:

input logic rst; // Should have been named rst_n

// Sequential logic with active-low reset
always_ff @(posedge clk or negedge rst) begin
    if (~rst) begin     // Again, should have used 'rst_n'
        // Reset logic
    end else begin
        // Normal operation
    end
end

See Correct Example

S12: No Initializers in Declarations

Rule: Do not write logic signal = 0;; instead, reset signals in an always_ff block.

Incorrect Example:

logic next_state = 0; // Not allowed, should be assigned in always_ff

See Correct Example

S13: Comments Before always_ff / always_comb

Rule: Each always_ff and always_comb block must be preceded by a comment describing its function.

Incorrect Example:

always_ff @(posedge clk) begin : always_ff_without_comment
    // No comment explaining function
end

always_comb begin : always_comb_without_comment
    // Also no comment explaining function
end

(Comments missing before always_ff / always_comb blocks.)

See Correct Example

S14: Comments Before Module Instantiation

Rule: Each module instantiation must have a comment explaining its purpose.

Incorrect Example:

clock_divider div_inst(
    .clk_in(clk),
    .clk_out(slow_clk)
);
some_module instanceName(
    .clk(clk),
    .rst(rst),
    .input1(input1),
    .output1(output1)
);

(Comments missing before each module instantiation.)

See Correct Example

S16: Assignment Operators in always_ff / always_comb

Rule: Use <= in always_ff, and = in always_comb or assign.

Incorrect Example:

always_ff @(posedge clk) begin
    regA = regB; // Using = in always_ff, should be <=
end

always_comb begin
    result <= opA + opB; // Using <= in always_comb, should be =
end

See Correct Example

S17: Default Assignments in always_comb

Rule: Every signal in always_comb must have a defined value.

Incorrect Example:

always_comb begin
    if (cond) begin
        next_state = 1;
    end
    // 'next_state' not assigned if `cond` is false, leading to inferred latch
end

(Always_comb should have a default assignment for all signals.)

See Correct Example

S18: Register Reset

Rule: Each always_ff must have a reset, clr, or load to set registers to known values.

Incorrect Example:

always_ff @(posedge clk) begin
    // No reset handling here; register starts unknown
    reg_data <= reg_data + 1;
end

(Registers should be reset to a known state on reset.)

See Correct Example

S19: One Register per always_ff

Rule: Don’t assign multiple unrelated registers in the same always_ff.

Incorrect Example:

// 'regA' and 'regB' are unrelated but assigned in one block
always_ff @(posedge clk) begin
    if (rst) begin
        regA <= 0;
        regB <= 0;
    end else begin
        regA <= nextA;
        regB <= nextB;
    end
end

(Unless they are a synchronizer or intimately related, this is a violation.)

See Correct Example

S20: Proper Reset Structure

Rule:

  • The if (rst) condition must always appear first in every always_ff block.
  • Never combine the initial reset condition with other signals using ||.
  • Handle secondary clear signals in the else branch after checking reset.
  • Place all subsequent sequential logic inside the else branch.

Incorrect Example:

// Reset incorrectly ORed with another signal
always_ff @(posedge clk) begin : always_block_with_rst_ORed
    if (rst || clrBit) begin
        data_reg <= 0;
    end else begin
        data_reg <= data_in;
    end
end

// Missing a `rst` condition
// Structure is `if-else if-else`, and not `if-else`
always_ff @ (posedge clk) begin : always_block_missing_rst
    if (clrTimer) begin
        timer <= 0;
    end else if (timerDone) begin
        timer <= 0;
    end else begin
        timer <= timer + 1; 
    end
end

// `rst` should not be used in always_comb.
// Instead use only default assignment
always_comb
begin
    // Defaults
    ns = cs;

    if (rst)
        ns = IDLE;
    else
        case (cs)
            IDLE:
                ...
            ...
        endcase
    end
end

See Correct Example

S21: Grouping Code by Submodules

Rule: Separate different functional logic sections with comments.

Incorrect Example:

// Next state logic
always_comb begin : next_state_logic
    // ...
end

// Timer register
always_ff @(posedge clk) begin : timer_register
    // ...
end

// State register
always_ff @(posedge clk) begin : state_register
    // ...
end

assign timer_done...

See Correct Example

S22: Local Signal Declarations

Rule: Signals declared immediately after module ports.

Incorrect Example:

module example_module(
    input logic clk,
    input logic rst
);
    // Internal Constants
    localparam MAX_COUNT = 255;
    
    // Internal Signals
    logic internalSignal;
    
    // Internal Register
    always_ff @(posedge clk or posedge rst) begin
        // ...
    end
    
    assign outputSignal = internalSignal == MAX_COUNT - 1;
    
    // More internal signals NOT declared at the top
    logic count_done;
    logic [3:0] counter; // Timer for ... (describe ambiguous signals)
    
    // Counter logic
    always_ff @(posedge clk) begin : counter_logic
        // ...
    end
    
    assign count_done = (counter == MAX_COUNT-1);
    
    // More internal signals NOT declared at the top
    // Internal State Machine
    typedef enum logic [1:0] {
        IDLE, RUNNING, DONE
    } state_t;
    state_t currentState, nextState;

    // ...
endmodule

See Correct Example

S23: Naming Conventions

Rule:

  • Use PascalCase or snake_case for module names.
  • Use camelCase or snake_case for signals.
  • Use UPPER_SNAKE_CASE for constants.
  • Keep naming conventions consistent.

Incorrect Example:

module TrafficLight_controller(  // Mixed naming style
    input logic cLock,           // Not in snake_case or consistent style
    input logic RST_signal
);
    localparam maxCount = 10; // Not using SCREAMING_SNAKE_CASE
    
    // Internal signals using inconsistent naming
    logic timer_done, bitCounter;
    logic BitDone; // internal signal using PascalCase, not camelCase or snake_case
    
    // ...
endmodule

See Correct Example