Lab 2: Vivado Tools

Table of Contents

In this lab you will learn how to use the Vivado tools that are necessary for synthesizing and generating bitstream files for the Basys3 FPGA development board.

The average time to complete this lab is 3.6 hours (however, the lab has changed substantially this year).

Learning Outcomes

  • Learn how to run the Vivado simulation tool and how to interact with the simulator
  • Learn how to run the Vivado synthesis tool and evaluate the synthesis output
  • Learn how to run the Vivado implementation tools and generate a bitstream file

Preliminary

The Basys3 board we are using in this class has a Field Programmable Gate Array (FPGA) from the “Artix7” family of FPGAs sold by AMD. AMD has provided a complex software tool suite called Vivado that is used to develop bitstreams implementing your digital logic that can be downloaded to the FPGA. The Vivado tool is a suite of tools that are used to create, simulate, synthesize, and implement designs for the FPGA. You will be using these tools throughout the semester, and it is necessary that you understand how to run these tools to complete your labs. This lab will guide you through the process of running the various Vivado tools on an example circuit to generate an FPGA bitstream. Like the previous lab, this lab will involve a lot of tutorials and reading, but it is important that you understand how to run these tools to be successful in the class.

The Vivado design tools contain a Graphical User Interface (GUI) for managing SystemVerilog files, projects, and simulation, as well as a command-line interface for most operations. However, in this class our use of the GUI will be limited;we will primarily use the command-line interface.

The Vivado tools are installed on the Digital Lab computers at the following path: /tools/Xilinx/Vivado/2024.1/. You will need to add the Vivado executable tools to your PATH and set up your terminal environment to run the tools. The following script will set up your terminal environment to run the Vivado tools:

source /tools/Xilinx/Vivado/2024.1/settings64.sh

If you find it annoying to type this full command each time you open a new terminal, you may consider adding a bash alias to your .bashrc. While you may be tempted to add this source command directly to your .bashrc, we advise against that, as it may interfere with tools you use in other classes.

Run the following command to make sure the Vivado tools are set up correctly:

vivado -version

What version of Vivado is being used in the Digital lab? Enter your result in the form 20xx.x

You can download a copy of the Vivado tools on your own computer. While you are welcome to run the tools on your computer, we cannot provide support for the Vivado tools on your computer. Even though you may be running the tools on your computer, all passoff scripts must run on the digital lab computers, and you must complete the passoff script on the digital lab computers.

Before starting the lab exercises make sure you have the latest startercode software updates by following the instructions here.

For this laboratory assignment you will be generating a circuit for the Basys3 board that performs binary addition between two 2-bit numbers. The numbers will be entered on the switches (switches [1:0] for the first operand and switches [3:2] for the second operand). Adding two 2-bit numbers will result in a 3-bit number which will be displayed on LEDs [2:0] on the Basys3 board.

A file named binary_adder.sv is included in the startercode for you that implements the binary addition logic in a SystemVerilog file. In future labs you will be required to create your own SystemVerilog files, but for this lab you will use the provided file. Open this file in VS Code to familiarize yourself with the code and to answer the question below. You will not need to edit this file for the lab exercises.

How many bits are there in the output this design?

How many gates are instanced in this SystemVerilog design?

Exercises

In this lab you will:

  • Exercise #1: Simulate the binary_adder.sv module, which adds two 2-bit binary numbers.
  • Exercise #2: Synthesize the binary_adder.sv module, and take some screenshots.
  • Exercise #3: Implement the binary_adder.sv module and download the bitstream to the Basys3 board.
  • Exercise #4: Fill in the logic_functions.sv module, test it with a testbench, and then program it onto the Basys3 board.

Exercise #1: Vivado Simulation

Logic simulation (sometimes called verification) is the most important phase of digital logic design. During logic simulation you test your design to verify that it functions as expected, before actually implementing it on hardware. Follow the Vivado Command Line Simulation Tutorial. This tutorial will introduce you to several Vivado executables and Tcl commands that are used to simulate your SystemVerilog files.

After completing the tutorial, run the binary adder in interactive simulation mode and determine the output of the LEDs for the following input combinations:

What is the value of O when the A=11 and B=01?

What is the value of O when the A=x1 and B=10?(x represents unknown)

Rather than having you manually run the various Vivado tools on the command-line, you will use Makefiles to run the various tools. Read the introductory section in the Shared Makefile Tutorial, up to and including the section on Simulation (Tcl Script).

Suppose for a given lab you are to create two hardware modules. How many Makefiles will your lab submission contain?

Most of the Makefile rules have already been created for you in a shared Makefile that you will include in your per-module Makefiles. we have created a Makefile that will run the necessary commands for you. This is a shared Makefile, that you will

Create a Tcl simulation script named sim.tcl (within the binary_adder/ directory) that will simulate the binary adder circuit. Write your script to test all sixteen different input combinations for the binary adder circuit. Your script should set the values of the switches, run the simulator to propagate the results, and read the values of the LEDs. When creating ‘Tcl’ files (or all code files that you submit), you must follow the ECEN 320 coding standards. Review these guidelines for ‘general files’ before submitting your script.

Run the following from within the binary_adder/ directory to run your simulation script. This should print the output values for all input combinations.

make sim_nogui

Include the file binary_adder/sim.tcl in your repository.

The Vivado simulator can also be run with a GUI for more visual interaction. Complete the Vivado GUI Simulation Tutorial. Make sure to update your sim.tcl file to include commands to set up the waveform viewer before running the simulation commands.

Run your simulation in GUI mode:

make sim

Take a screenshot of your simulation and save it in the file binary_adder/sim.png (instructions for taking screenshots are here). Note that you must follow the screenshot guidelines listed in the tutorial to avoid penalty.

Include the file binary_adder/sim.png in your repository.

Exercise #2: Vivado Synthesis

The next step of the design process is to synthesize your design, which converts your SystemVerilog code into a set of connected logic gates (called a netlist) that can be implemented on the FPGA. Unlike the simulation tools which can be used to simulate logic for any target hardware, the synthesis tools are specific to the target FPGA you are using on the Basys3 board. In this exercise you will:

  • Generate a pre-synthesis schematic
  • Perform synthesis to covert the binary_adder.sv into a netlist for the AMD Artix7 FPGA
  • Generate a post-synthesis schematic

Pre-Synthesis Schematic

Look over the Pre-Synthesis Schematic Section of the Common Makefile Tutorial and generate a pre-synthesis schematic of the binary_adder module. Save a screenshot of the schematic as binary_adder/pre-synth-schematic.png.

Include the file binary_adder/pre-synth-schematic.png in your repository.

How many gates are shown in this schematic?

Which types of gates are shown in this diagram? Select all that apply

Logic Synthesis

Look over the Logic Synthesis Section of the Common Makefile Tutorial and synthesize the binary_adder module. Carefully review the synthesis log and answer the following questions:

How many total LUT resources are used by the design? (add up all the LUT2, LUT3, LUT4, LUT5, and LUT6 resources)

Post-Synthesis Schematic

Look over the Post-Synthesis Schematic Section of the Common Makefile Tutorial and generate a post-synthesis schematic of the binary_adder module. Save the screenshot as binary_adder/post-synth-schematic.png within your repository.

Include the file binary_adder/post-synth-schematic.png in your repository.

How many LUT primitives are listed in the ‘Netlist Properties’ pane of the post-synthesis schematic viewer?

How many IO primitives are listed in the ‘Netlist Properties’ pane of the post-synthesis schematic viewer?

Note that the post-synthesis schematic uses different cells than the pre-synthesis schematic. In the pre-synthesis schematic generic gates were used. In the post-synthesis schematic Look Up Tables (LUT) were used as these are the resources available on the FPGA.

Exercise #3: Vivado Implementation and Bitstream Download

After the design has been successfully synthesized, it needs to be implemented onto the FPGA and converted into a bitstream that can be downloaded onto the FPGA.

Look over the Implementation Section of the Common Makefile Tutorial, and run the implementation process for the binary_adder module. Look in the utilization.rpt file to answer the following:

How many Slice LUTs are used by the design?

Finally, download the generated bitstream file to the Basys3 board and test the operation of the design on the board. There is a shortcut Makefile rule to make this easy:

make download

Exercise 4: Write and implement the logic_functions module

  1. Finish writing the SystemVerilog module logic_functions.sv in the logic_functions/ directory. This module should implement the logic functions:
    • O1 = AC+A’B
    • O2 = (A+C’)(BC)

    You must use only basic logic gates (and, or, not) to implement these functions.
    If these functions require intermediate signals (signals that are not module ports), you will need to declare them using the ‘logic’ keyword (see text for details). Also, choose meaningful names or (probably better yet) put a comment above them to tell what they are used for.

  2. Create a Makefile (logic_functions/Makefile). Copy the Makefile from the binary_adder/ directory and modify it for the logic_function module.

  3. Using Tcl files in an interactive simulation environment is a good way to find errors early in the simulation phase. However, it is difficult to fully test complex digital circuits with Tcl files. A more thorough way to test your digital circuit is to use a special SystemVerilog module called a testbench. You are provided with a testbench file tb.sv that will test your module.

    Look over the Simulation (Testbench) Section of the Common Makefile Tutorial and simulate your logic_functions module using the provided testbench.

    What is the time in nano seconds in which the simulation ends?

    What are the values of A,B,C at time 140ns in the testbench simulation?

  4. View the pre-synthesis schematic of your logic_functions module, and save the screenshot as logic_functions/pre-synth-schematic.png within your repository.

    Include the file logic_functions/pre-synth-schematic.png in your repository.

  5. Run make download, which should trigger synthesis, implementation, and download the bitstream to the Basys3 board. A logic_functions/basys3.xdc file is provided that maps A, B, and C to switches 2, 1, and 0 respectively, and maps O1 and O2 to LEDs 1 and 0 respectively. Test your design on the Basys3 board to verify that it works correctly.

Pass-Off

Refer to the passoff tutorial for the passoff process.

  • See required_files in the passoff script.
  • Makefile rules that must work correctly and be free from errors and warnings:
    • Makefile: clean
    • binary_adder/Makefile: sim_nogui, synth, implement
    • logic_functions/Makefile: sim_tb, synth, implement

Answer the final two questions in your laboratory report:

How many hours did you work on the lab?

Provide any suggestions for improving this lab in the future