In this lab you will learn what a seven-segment display is and how it works. You will create a digital circuit that drives a seven-segment display with hexadecimal characters.

The average time to complete this lab is 4 hours.

Learning Outcomes

• Learn how a seven-segment display works.
• Create a seven-segment decoder digital circuit.
• Learn how to use SystemVerilog dataflow operators.
• Learn how to validate your circuit with a testbench.

Vivado Issues - There is Help Available

At this point in the semester, you are getting familiar with Vivado. If you are one of the unlucky ones you may have had Vivado hang when you try to simulate or synthesize. You need to learn about how to debug and fix it when that happens.

The page Taming Vivado gives detailed instructions on what to do in these cases.

Go read it now. Then, read it again. Then, if you don’t understand some of the things it recommends, visit with a TA before you proceed. This is IMPORTANT!

Preliminary

The Basys 3 board contains a 4-digit, seven-segment display as shown below. This display can be used to display any information you desire, such as a counter value, register values, a timer, etc. In this week’s lab you will create a circuit to drive one digit of this display. Later in the semester, we will provide you with a module to drive all of the four digits at once. It will use the display module created in this lab. You will then use that full display in a number of labs as a way to display numerical information.

Before designing a seven-segment controller circuit, it is necessary to understand how the seven-segment display operates. As the name implies, a seven-segment display has seven discrete segments that can each be individually turned on to make a variety of different characters. Each of the seven segments are labeled with a letter as shown in the image below:

For example, the character “0” can be displayed on the seven-segment display by turning on segments a, b, c, d, e, f, and turning off segment g.

Each segment of the seven-segment display is driven by an individual LED (light-emitting diode). The schematic diagram below shows these LEDs used by a seven-segment display. In addition to the seven segments for displaying a character, many displays include an eighth LED for the digit point (the dot to the bottom right of the seven segments). This is commonly abbreviated to DP as seen below.

In this configuration, all eight LEDs share a common anode which enables the display. Each segment has its own cathode signal labeled CX where X represents the segment letter. For example, signal CA corresponds to the cathode signal for segment a.

To turn on an LED, there must be a sufficient voltage drop from anode to cathode. That is, the anode needs to have a high voltage (‘1’) and the cathode has to have a low voltage (‘0’). Go back and read that last sentence again - what do you drive onto a cathode wire to turn a segment on?

To display the character 0, the anode signal will have a high voltage, the cathode signals CA, CB, CC, CD, CE, and CF will have a low voltage, and the cathode signal CG will have a high voltage.

Although any arbitrary combination of segments can be turned on, digital circuits are often created to display the 16 different characters representing any 4-bit value in hexadecimal. These characters are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F. Each of these is shown in the image below.

Before you can create a circuit to display these hexadecimal characters, you need to determine the value each cathode signal needs for each character.

Fill out the decoder table below so that the segment outputs on each row will display the number given by that row’s hexadecimal character. Also included in this table is the binary representation of each hexadecimal character in the D columns. The first row of the table is completed and shows the segments that will be active for an input of 0. Carefully look at the top entry (which will display a ‘0’ digit) to make sure you understand.

Decoder Table

After filling in the decoder table for a seven-segment display:

1. Provide the requested segment values from the decoder table.
2. Provide a logic equation for segment A (CA).

If you’re confused about how to make an equation for a segment, remember that a whole column represents an individual output. Simply pick the column for the segment as labeled in the table as a truth table output and read off the equation.

On Learning Suite, you will only have to fill in a few sections of this table. But, make sure that your entire table is correct – it will make the rest of this lab much easier.

The Board’s 7 Segments

The seven-segment display on the Basys 3 board has four unique digits as shown below.

Each digit of the four-digit display has its own anode input (A0-A3). NOTE however, that there is a built-in inverter on each anode signal. Thus, to turn on any of the segments of a digit, its corresponding anode and cathode signals must both be driven LOW. The schematic of this four-digit, seven-segment display is shown below.

This four-digit, seven-segment display configuration is known as a common cathode arrangement because the cathode signals are shared among all four digits. If more than one anode signal is asserted low, the corresponding digits will have the same segments turn on because they are connected to the same cathode signals. While this significantly reduces the pin count, it makes it difficult to display different values simultaneously. (Different values can be displayed by quickly switching between the various anode and cathode signals — the LED’s will flash so quickly your eye will see them as all being “on”. This is called “time-multiplexing” the digits. You will be given a time-multiplexing seven-segment display controller to use in future laboratory assignments.)

For example, to turn on only the right two digits of the four digit display, AN1 and AN0 must have a logic value of 0 and the other anode signals must have a logic value of 1.

In the following example, two of the digits are turned on by setting their corresponding anode to zero. The other digits are off since their anode signals are set to one. In addition, the digit 3 is displayed based on which cathode signals have a logic 0. The digit point is also on since the cathode signal, DP, associated with the digit point is set to 0.

What would happen if all four anode control signals were set to a logic value of 0 simultaneously in the example above?

Determine what will be shown on the display with the following signal values.

Exercises

Exercise #1 - Seven-Segment SystemVerilog

In this exercise you will create a seven-segment decoder in a SystemVerilog module. You will create the logic for just one digit. Begin by creating a new Vivado project like you did in the previous lab (you will create a new project for each laboratory assignment). Remember to always follow the steps in the Project Configuration section to properly configure the error messages and other settings in your project. Also remember to use the correct FPGA part number.

After creating this project, create a new SystemVerilog file with the following module name and ports:

Review the page on Combinational Logic Styles since you are going to be required to implement each segment using a different SystemVerilog coding style. Note that for this lab you need not use always_comb blocks so you can skip those for now. But, you will use them in future labs so remember this page so you can go back there to review them when the time comes.

Create the logic necessary for your cathode segments (CA to CG) (for this circuit, you will not create logic for the digit point (segment[7])).

You are required to use a mix of combinational logic styles. For your seven segments, you must have at least one segment that uses each of the following styles:

• Structural SV (gates like in Lab 3), in non-minimized, sum-of-products form.
• Structural SV, minimized using the theorems in Table 4.1 of the textbook.
• Dataflow SV, using an assign statement and the ?: (sometimes called the ternary) operator.
• Dataflow SV, using an assign statement and dataflow operators of your choice (comparison, and, or, etc.).

Once you have completed the logic for your seven-segment decoder, proceed with the simulation of your module using a Tcl script. Your Tcl file should simulate all 16 possible digits to see if the output of your module matches that seven-segment decoder table you created above.

Include your Tcl simulation file in your report.

Exercise 1 Pass-off: Show a TA your SV code, Tcl commands and simulation.

Exercise #2 - Verification with a Testbench

A testbench circuit has been created for you in this lab to test your seven-segment decoder. Test your seven-segment decoder circuit using the testbench by following these steps.

1. Download the tb_sevensegment.v testbench file.
2. If needed, review the Adding a Testbench and Simulating with a Testbench tutorial.
3. Add the testbench to your project (as a simulation source file).
4. Start simulating the testbench and carefully view the messages. If you have errors, carefully debug these errors and simulate again until you have no errors. When you pass the testbench without any errors, you are ready to proceed to the next exercise.

Copy and paste the testbench console output into your report (the console should report no errors).

Exercise 2 Pass-off: Nothing to pass off, just be sure it is passing the testbench.

Exercise #3 - Top-Level Design

Begin this exercise by creating a second SystemVerilog file with the following module name and ports:

The figure below demonstrates the structure of this top-level design. You will also create some additional logic in this top-level design.

Instance Seven-Segment Decoder Module

Begin your top-level module by instancing the seven-segment display module you created in the previous exercise.

Connect the four-bit switch input ports from your top-level design to the data inputs of your seven-segment display. Connect the 7 segment bits (segment[6:0]) from your seven-segment display outputs to bits [6:0] of the top-level segment output.

Digit Point

Your seven-segment decoder module drives seven of the eight cathode segment signals (segment[6:0]). The eighth segment signal (segment[7]) is used for the “digit point”. You need to create logic to turn on the digit point (DP or segment[7]). For this top-level design, we want to turn on the digit point when btnc is pressed. Create a logic circuit using structural SystemVerilog in your top-level module for the digit point based on the value of btnc. Remember that the cathode segment signals are turned on when the logic value of 0 is given.

Anode Signals

The last component of your top-level design is the logic to drive the anode signals. For this top-level design, you will need to create logic that turns on the right most digit (associated with anode[0]) and turn off the other three digits (anode[3:1]). To turn on the right most digit, we simply need to assign the ‘anode’ output with a constant value (reread above if needed to learn what constant value to use). Add a dataflow assign statement in your top-level SystemVerilog file to assign the anode signals such that only the right most digit is turned on. The following SystemVerilog statement can be added to set the anode signals (you will need to replace the “X” values with actual ‘1’s or ‘0’):

assign anode = 4'bXXXX;

After completing your top-level design, simulate it to make sure your digit point (DP) logic and your anode logic is correct. Also, simulate all possible data inputs to verify your top-level circuit is working properly.

Paste your top-level module SystemVerilog code.

Attach a screenshot of your working simulation waveform to Learning Suite.

Exercise 3 Pass-off: Nothing to pass off - just answer the questions above.

Exercise #4 - Implement and Download

Begin this process by creating and adding an XDC constraints file. Do this like you have done in previous labs. Remember, the easiest way to create this file is to start with the master .xdc file and modify it.

Once you have the XDC file added to your project, synthesize your project.

Provide a summary of your synthesis warnings and an explanation of why they do or do not matter (be careful – it will be rare when a warning can be ignored, but it does happen; you just need to figure out when that is).

Implement your module.

Indicate the number of LUTs and I/O pins your design uses.

You can find this in the the Utilization box within the “Project Summary” window (use the “Post-Implementation” tab).

Generate a bitfile for your design, download your circuit, and verify that it works as expected.

Final Pass-Off:

Do the pass-off in person with a TA or by video:

Show your circuit working correctly on the board and explain what you are doing. Show that it displays digits properly as you manipulate the switches and btnc.

Explain (in some detail) why you aren’t able to display two different numbers on two different digits at the same time on the display.

Final Questions

Paste your ‘seven_segment’ SystemVerilog module code.

And, as always, make sure your SystemVerilog conforms to the lab SystemVerilog coding standards.

How many hours did you work on the lab?

Provide any suggestions for improving this lab in the future.