In this lab you will learn how to use the Vivado tools that are necessary for synthesizing and generating bitstream files for the Basys3 FPGA development board.

Learning Outcomes

• Learn how to run the Vivado simulation tool and how to interact with the simulator
• Learn how to run the Vivado synthesis tool and evaluate the synthesis output
• Learn how to run the Vivado implementation tools and generate a bitstream file

Preliminary

The Basys3 board we are using in this class has a Field Programmable Gate Array (FPGA) from the “Artix7” family of FPGAs sold by AMD. AMD has provided a complex software tool suite called Vivado that is used to develop bitstreams implementing your digital logic that can be downloaded to the FPGA. The Vivado tool is a suite of tools that are used to create, simulate, synthesize, and implement designs for the FPGA. You will be using these tools throughout the semester, and it is necessary that you understand how to run these tools to complete your labs. This lab will guide you through the process of running the various Vivado tools on an example circuit to generate an FPGA bitstream. Like the previous lab, this lab will involve a lot of tutorials and reading, but it is important that you understand how to run these tools to be successful in the class.

The Vivado tools are installed on the Digital Lab computers at the following path: /tools/Xilinx/Vivado/2024.1/. You will need to add the Vivado executable tools to your path and set up your terminal environment to run the tools. The following script will set up your terminal environment to run the Vivado tools:

source /tools/Xilinx/Vivado/2024.1/settings64.sh

You may want to add this line to your .bashrc file so that the Vivado tools are set up every time you open a terminal.

Run the following command to make sure the Vivado tools are set up correctly:

vivado -version

What version of Vivado is being used in the Digital lab? Enter your result in the form 20xx.x

You can download a copy of the Vivado tools on your own computer. While you are welcome to run the tools on your computer, we cannot provide support for the Vivado tools on your computer. Even though you may be running the tools on your computer, all passoff scripts must run on the digital lab computers, and you must complete the passoff script on the digital lab computers.

Before starting the lab exercises make sure you have the latest ‘startercode’ software updates by following the instructions here.

For this laboratory assignment you will be generating a circuit for the Basys3 board that performs binary addition between two 2-bit numbers. The numbers will be entered on the switches (switches [1:0] for the first operand and switches [3:2] for the second operand). Adding two 2-bit numbers will result in a 3-bit number which will be displayed on LEDs [2:0] on the Basys3 board.

A file named binary_adder.sv is included in the startercode for you that implements the binary addition logic in a ‘SystemVerilog’ file. In future labs you will be required to create your own SystemVerilog files, but for this lab you will use the provided file. Open this file in VSCode to familiarize yourself with the code and to answer the question below. You will not need to edit this file for the lab exercises.

How many bits are there in the output this design?

How many gates are instanced in this SystemVerilog design?

Exercise #1 - Vivado Simulation

Logic simulation is an essential step in the design of complex digital circuits. During logic simulation you will simulate the logic of your design to verify that it functions as expected. Logic simulation (sometimes called verification) is the most important phase of digital logic design. Sophisticated tools have been developed to help you properly simulate your logic. In this exercise you will learn how to use the Vivado simulation tools to simulate the binary adder circuit.

The Vivado design tools contain a Graphical User Interface (GUI) for managing SystemVerilog files, projects, and simulation. We will not use the GUI for this class but will instead use the command line tools, Tcl scripts, and Makefile rules to implement the simulation steps. Begin the simulation process by following the Vivado Command Line Simulation Tutorial. This tutorial will introduce you to several Vivado executables and Tcl commands that are used to simulate your SystemVerilog files.

After completing the tutorial, run the binary adder in interactive simulation mode and determine the output of the LEDs for the following input combinations:

What is the value of ‘O’ when the A=11 and B=01?

What is the value of ‘O’ when the A=x1 and B=10?(‘x’ represents unknown)

Create a Tcl simulation script named sim_adder.tcl that will simulate the binary adder circuit. Write your script to test all sixteen different input combinations for the binary adder circuit. Your script should set the values of the switches, run the simulator to propagate the results, and read the values of the LEDs. When creating ‘Tcl’ files (or all code files that you submit), you must follow the ECEN 320 coding standards. Review these guidelines for ‘general files’ before submitting your script.

Include the file sim_adder.tcl in your lab repository.

Match the executable name with the function (xelab, xvlog, xsim)

The Vivado simulator can also be run with a GUI for more visual interaction. Complete the Vivado GUI Simulation Tutorial to learn how to use the Vivado Simulator GUI. When you have learned how to run the GUI simulator, run the simulation script sim_adder.tcl created earlier to generate a waveform of your simulation running your simulation script. Take a screenshot of your simulation and save it in the file sim_waveform.png (instructions for taking screenshots are here). Note that you must follow the screenshot guidelines listed in the tutorial to avoid penalty.

Include the file sim_waveform.png in your lab repository.

Exercise #2 - Vivado Synthesis

Once a design has been verified using the simulation tools, the next step in the process is to ‘synthesize’ the SystemVerilog files into a format that can be used within the FPGA. Specifically, the synthesis tool will convert the logic equations into specific logic resources on the FPGA circuit (or whatever logic target you are using). Unlike the simulation tools which can be used to simulate logic for any target hardware, the synthesis tools are specific to the target FPGA you are using on the Basys3 board. In this exercise you will learn how to use the Vivado synthesis tools to generate a ‘pre-synthesis’ schematic, covert the binary adder SystemVerilog circuit into a netlist for the AMD Artix7 FPGA, and how to generate a ‘post-synthesis’ schematic.

Like simulation, the synthesis tools will perform ‘HDL analysis’ and ‘HDL Elaboration’. The tools for synthesis, however, are different from the tools used for simulation.

Pre-Synthesis Schematic

It is often helpful to view a “schematic” or structural representation of the circuit you are designing. In this exercise you will be creating three different schematics: a pre-synthesis schematic, a post-synthesis schematic, and a post-implementation schematic. Each of these schematics will be different and represent your design in different stages of the design flow. You will use the Vivado tools to generate these schematics.

Once your circuit is simulating correctly, you can create a schematic of the circuit before you start the synthesis step. Complete the first part of the Vivado Schematic Tutorial to generate a schematic of the HDL binary adder design (do not move on to the post-schematic section of this tutorial until later). After completing this tutorial, take a screenshot of the schematic and save it in the file pre-synth-schematic.png within your repository.

Include the file pre-synth-schematic.png in your lab repository.

How many gates are shown in this schematic?

Which types of gates are shown in this diagram? Select all that apply

Logic Synthesis

Logic synthesis is an essential step that will convert your design from its original HDL format (as seen in the pre-synthesis schematic) into a netlist using FPGA logic resources. Begin the logic synthesis process by following the Vivado Command Line Synthesis Tutorial. After completing the synthesis tutorial, create a Tcl script named synth_adder.tcl that will run the synthesis process and a Makefile rule named synth_adder that will run the Tcl script in batch mode. The rule should also create a file named synth_adder.log that contains the output of the synthesis process, and the Tcl script should generate a file named binary_adder_synth.dcp that contains the checkpoint file for your synthesized design. Make sure your synthesis script includes the source ../resources/messages.tcl command to set the message severity levels for the synthesis tool.

Carefully review the synthesis log and answer the following questions:

How many total LUT resources are used by the design? (add up all the LUT2, LUT3, LUT4, LUT5, and LUT6 resources)

Post-Synthesis Schematic

After successfully generating a ‘.dcp’ file from the synthesis step, generate a schematic of the post-synthesis design by completing the second half of the Vivado Schematic Tutorial. This schematic will look very different from the ‘pre-synthesis’ schematic as it converts the gate-level representation into a representation for use in the FPGA. Take a screenshot of this schematic and name it post-synth-schematic.png.

Include the file post-synth-schematic.png in your lab repository.

How many LUT primitives are listed in the ‘Netlist Properties’ pane of the post-synthesis schematic viewer?

How many IO primitives are listed in the ‘Netlist Properties’ pane of the post-synthesis schematic viewer?

Note that the post-synthesis schematic uses different cells than the pre-synthesis schematic. In the pre-synthesis schematic generic gates were used. In the post-synthesis schematic Look Up Tables (LUT) were used as these are the resources available on the FPGA.

Exercise #3 - Vivado Implementation and Bitstream Download

After the design has been successfully synthesized, it needs to be “implemented” onto the FPGA and converted into a bitstream that can be downloaded onto the FPGA. Begin the implementation process by following the Vivado Command Line Implementation Tutorial.

After completing the synthesis tutorial, create a Tcl script named implement_adder.tcl that will run the implementation process and a Makefile rule named implement_adder that will run the Tcl script in batch mode. The rule should also create a file named implement_adder.log that contains the output of the implementation process, and the Tcl script should generate a file named binary_adder.bit that will be uploaded to the board to configure the FPGA, a file named binary_adder.dcp that contains the final design checkpoint, and a file named utilization.rpt that contains the utilization report for your design.

How many Slice LUTs are used by the design?

The final step involves downloading the bitstream file to the Basys3 board and testing the operation of the design on the board. Follow the steps described in the Bitstream Download Tutorial to download the bitstream file to the Basys3 board (this should be review as you completed this step in the previous lab).

Pass-Off

Make sure you have the following required files in your repository and Makefile rules implemented before you pass off this lab. Refer to the passoff tutorial for questions about the passoff process.

• Required Files
  • sim_adder.tcl
  • sim_waveform.png
  • pre-synth-schematic.png
  • post-synth-schematic.png
  • Makefile (this file is required for all assignments and will not be listed in future labs)
  • .gitignore (this file is required for all assignments and will not be listed in future labs)
• Required Makefile ‘rules’
  • synth_adder: requires synth_adder.tcl, generates synth_adder.log, binary_adder_synth.dcp
  • implement_adder: requires implement_adder.tcl, binary_adder_synth.dcp, generates implement_adder.log, binary_adder.dcp, binary_adder.bit, utilization.rpt
  • clean (this rule is required for all assignments and will not be listed in future labs)

Answer the final two questions in your laboratory report:

How many hours did you work on the lab?

Provide any suggestions for improving this lab in the future