ECEn 320
Learning Suite Teams Submission Coding Standards Help Queue
Labs
1 Basys3 Introduction 2 Vivado Tools 3 Structural SystemVerilog 4 Arithmetic 5 Seven Segment 6 Register File 7 Multi-Segment Display 8 VGA Controller 9 Debouncer 10 UART Transmitter 11 UART Receiver 12 Character Display 13 Codebreaker
Resources
All Documentation Lab Instructions Git Basics Error Messages Vivado Tutorials   Simulation (CL)   Simulation (GUI)   Simulation (Testbench)   Synthesis   Schematic   Implementation

All Documentation

Table of Contents

  • General
  • Tools
  • Basys3
  • Vivado
  • Design Examples

General

  • Laboratory Assignment Instructions
  • Accessing computers remotely
  • Digital Lab Policies
  • Selecting the Display Video Input

Tools

  • Linux Command Summary
  • VS Code
  • Putty
  • Screen Capture with OBS
  • Git
    • Setting up your GitHub Classroom Repository
    • Setting up a GitHub SSH Key
    • Cloning your classroom repository
    • Git Basics
  • Installing Vivado Locally

Basys3

  • Basys3 Overview (with video)
  • Downloading Bitfiles
  • Basys 3 Reference Manual
  • Basys 3 Schematics
  • Constraints File: basys3_220.xdc

Vivado

  • Vivado Simulation Tutorial
  • Vivado GUI Simulation Tutorial
  • Vivado Synthesis Tutorial
  • Vivado Schematic Tutorial
  • Vivado Implementation Tutorial

  • Creating XDC files
  • Viewing FPGA Design Layout
  • Simulating with Testbenches
  • Viewing Schematic Hierarchy
  • Simulation Hints
  • Common Error Messages

Design Examples

  • Combinational Logic Styles
  • Coding Standards - Good Examples
  • Coding Standards - Bad Examples